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| cy14e256la 256-kbit (32 k 8) nvsram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-54952 rev. *j revised september 28, 2012 256-kbit (32 k 8) nvsram features 25 ns and 45 ns access times internally organized as 32 k 8 (cy14e256la) hands-off automatic store on power-down with only a small capacitor store to quantumtrap nonvolatile elements initiated by software, device pin, or autostore on power-down recall to sram initiated by software or power-up infinite read, write, and recall cycles 1 million store cycles to quantumtrap 20-year data retention single 5 v + 10% operation industrial temperature 44-pin thin small-outline package (tsop) type ii and 32-pin small-outline integrated circuit (soic) package pb-free and restriction of hazardous substances (rohs) compliant functional description the cypress cy14e256la is a fast static ram, with a nonvolatile element in each memory cell. the memory is organized as 32 kb. the embedded nonvolatile elements incorporate quantumtrap technology, producing the world?s most reliable nonvolatile memory. the sram provides infinite read and write cycles, while independent nonvolatile data resides in the highly reliable quantumtrap cell. data transfers from the sram to the nonvolatile elements (the store operation) takes place automatically at power-down. on power-up, data is restored to the sram (the recall operation) from the nonvolatile memory. both the store and recall operations are also available under software control. store/ recall control power control software detect static ram array 512 x 512 quantumtrap 512 x 512 store recall column i/o column dec row decoder input buffers oe ce we hsb v cc v cap a 13 - a 0 a 0 a 1 a 2 a 3 a 4 a 10 a 5 a 6 a 7 a 8 a 9 a 12 a 13 a 14 dq 0 dq 1 dq 2 dq 3 dq 4 dq 5 dq 6 dq 7 a 11 logic block diagram
cy14e256la document number: 001-54952 rev. *j page 2 of 19 contents pinouts .............................................................................. 3 pin definitions .................................................................. 3 device operation .............................................................. 4 sram read ................................................................ 4 sram write ................................................................. 4 autostore operation .................................................... 4 hardware store operation ....................................... 4 hardware recall (power-up) ................................... 5 software store ......................................................... 5 software recall ....................................................... 5 preventing autostore .................................................. 6 data protection ............................................................ 6 maximum ratings ............................................................. 7 operating range ............................................................... 7 dc electrical characteristics .......................................... 7 data retention and endurance ....................................... 8 capacitance ...................................................................... 8 thermal resistance .......................................................... 8 ac test loads .................................................................. 9 ac test conditions .......................................................... 9 ac switching characteristics ....................................... 10 sram read cycle .................................................... 10 sram write cycle ..................................................... 10 switching waveforms .................................................... 10 autostore/power-up recall ....................................... 12 switching waveforms .................................................... 12 software controlled store/recall cycle ................ 13 switching waveforms .................................................... 13 hardware store cycle ................................................. 14 switching waveforms .................................................... 14 truth table for sram operations ................................ 15 ordering information ...................................................... 15 ordering code definitions ..... .................................... 15 package diagrams .......................................................... 16 acronyms ........................................................................ 17 document conventions ................................................. 17 units of measure ....................................................... 17 document history page ................................................. 18 sales, solutions, and legal information ...................... 19 worldwide sales and design s upport ......... .............. 19 products .................................................................... 19 psoc solutions ......................................................... 19 cy14e256la document number: 001-54952 rev. *j page 3 of 19 pinouts figure 1. 44-pin tsop ii / 32-pin soic pinout nc a 8 nc nc v ss dq 6 dq 5 dq 4 v cc a 13 dq 3 a 12 dq 2 dq 1 dq 0 oe a 9 ce nc a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 11 a 7 a 14 nc nc nc nc nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 top view (not to scale) a 10 nc we dq 7 hsb nc v ss v cc v cap nc (x 8) [4] [5] [2] [3] [1] [1] 44-pin tsop ii 32-pin soic (x 8) top view (not to scale) pin definitions pin name i/o type description a 0 ?a 14 input address inputs. used to select one of the 32,768 bytes of the nvsram. dq 0 ?dq 7 input/output bidirectional data i/o lines. used as input or output lines depending on operation. we input write enable input, active low. when the chip is enabled and we is low, data on the i/o pins is written to the specific address location. ce input chip enable input, active low. when low, selects the chip. when high, deselects the chip. oe input output enable, active low. the active low oe input enables the data output buffers during read cycles. i/o pins are tri-stated on deasserting oe high. v ss ground ground for the device. must be connected to the ground of the system. v cc power supply power supply inputs to the device. hsb input/output hardware store busy (hsb ). when low, this output indicates t hat a hardware store is in progress. when pulled low, external to the chip, it initiate s a nonvolatile store operation. after each hardware and software store operation hsb is driven high for a short time (t hhhd ) with standard output high current and then a weak internal pull-up resistor keep s this pin high (external pull-up resistor connection is optional). v cap power supply autostore capacitor. supplies power to the nvsram during power loss to store data from sram to nonvolatile elements. nc no connect no connect. this pin is not connected to the die. notes 1. address expansion for 1-mbit. nc pin not connected to die. 2. address expansion for 2-mbit. nc pin not connected to die. 3. address expansion for 4-mbit. nc pin not connected to die. 4. address expansion for 8-mbit. nc pin not connected to die. 5. address expansion for 16-mbit. nc pin not connected to die. cy14e256la document number: 001-54952 rev. *j page 4 of 19 device operation the cy14e256la nvsram is made up of two functional components paired in the same physical cell. they are an sram memory cell and a nonvolatile quantumtrap cell. the sram memory cell operates as a standard fast static ram. data in the sram is transferred to the nonvolatile cell (the store operation), or from the nonvolatile cell to the sram (the recall operation). using this unique arch itecture, all cells are stored and recalled in parallel. during the store and recall operations, sram read and write operations are inhibited. the cy14e256la supports infinite reads and writes similar to a typical sram. in addition, it provides infinite recall operations from the nonvolatile cells and up to 1 million store operations. refer to the truth table for sram operations on page 15 for a complete description of read and write modes. sram read the cy14e256la performs a read cycle when ce and oe are low and we and hsb are high. the address specified on pins a 0-14 determines which of the 32,768 data bytes each are accessed. when the read is in itiated by an address transition, the outputs are valid after a delay of t aa (read cycle 1). if the read is initiated by ce or oe , the outputs are valid at t ace or at t doe , whichever is later (read cycle 2) . the data outp ut repeatedly responds to address changes within the t aa access time without the need for transitions on any control input pins. this remains valid until another address change or until ce or oe is brought high, or we or hsb is brought low. sram write a write cycle is performed when ce and we are low and hsb is high. the address inputs must be stable before entering the write cycle and must re main stable until ce or we goes high at the end of the cycle. the dat a on the common i/o pins dq 0?7 are written into the memory if the data is valid t sd before the end of a we -controlled write or bef ore the end of a ce -controlled write. keep oe high during the entire wr ite cycle to avoid data bus contention on common i/o lines. if oe is left low, internal circuitry turns off the output buffers t hzwe after we goes low. autostore operation the cy14e256la stores data to the nvsram using one of the following three storage operations: hardware store activated by hsb; software store activated by an address sequence; autostore on device power-down. the autostore operation is a unique feature of quantumtrap technology and is enabled by default on the cy14e256la. during a normal operation, the device draws current from v cc to charge a capacitor connected to the v cap pin. this stored charge is used by the chip to perform a single store operation. if the voltage on the v cc pin drops below v switch , the part automatically disconnects the v cap pin from v cc . a store operation is initiated with power provided by the v cap capacitor. note if the capacitor is not connected to v cap pin, autostore must be disabled using the soft sequence specified in preventing autostore on page 6 . in case autostore is enabled without a capacitor on v cap pin, the device attempts an autostore operation without sufficient char ge to complete the store. this corrupts the data stored in nvsram. figure 2 shows the proper connection of the storage capacitor (v cap ) for automatic store operation. refer to dc electrical characteristics on page 7 for the size of v cap . the voltage on the v cap pin is driven to v cc by a regulator on the chip. place a pull-up on we to hold it inactive during power-up. this pull-up is only effective if the we signal is tristate during power-up. many mpus tristate their controls on power-up. this mu st be verified when using the pull-up. when the nvsram comes out of power-on-recall, the mpu mu st be active or the we held inactive until the mp u comes out of reset. to reduce unnecessary nonvolatile stores, autostore and hardware store operations are ignored unless at least one write operation has taken place since the most recent store or recall cycle. software initiat ed store cycles are performed regardless of whether a write operation has taken place. the hsb signal is monitored by the syst em to detect if an autostore cycle is in progress. figure 2. autostore mode hardware store operation the cy14e256la provides the hsb pin to control and acknowledge the store operations. use the hsb pin to request a hardware store cycle. when the hsb pin is driven low, the cy14e256la conditionally initiates a store operation after t delay . an actual store cycle only begins if a write to the sram has taken place since the last store or recall cycle. the hsb pin also acts as an open drain driver (internal 100 k ? weak pull-up resistor) that is internally driven low to indicate a busy condition when the store (initiated by any means) is in progress. note after each hardware and software store operation hsb is driven high for a short time (t hhhd ) with standard output high current and then remains high by internal 100 k ? pull-up resistor. sram write operations that are in progress when hsb is driven low by any means are given time (t delay ) to complete before the store operation is initiated. however, any sram write cycles requested after hsb goes low are inhibited until hsb returns high. in case the write latch is not set, hsb is not driven low by the cy14e256la. but any sram read and write cycles are inhibited until hsb is returned high by mpu or other external source. 0.1 uf v cc 10 kohm v cap we v cap v ss v cc cy14e256la document number: 001-54952 rev. *j page 5 of 19 during any store operation, rega rdless of how it is initiated, the cy14e256la continues to drive the hsb pin low, releasing it only when the store is comp lete. upon completion of the store operation, the nvsram memory access is inhibited for t lzhsb time after hsb pin returns high. leave the hsb unconnected if it is not used. hardware recall (power-up) during power-up or after any low power condition (v cc cy14e256la document number: 001-54952 rev. *j page 7 of 19 maximum ratings exceeding maximum ratings may shorten the useful life of the device. these user guidelines are not tested. storage temperature ..... ............ ............... ?65 ? c to +150 ? c maximum accumulated storage time: at 150 ? c ambient temperature ...................... 1000 h at 85 ? c ambient temperature .................... 20 years maximum junction temperature .................................. 150 ? c supply voltage on v cc relative to v ss ...........?0.5 v to 7.0 v voltage applied to outputs in high z state ........................ ?0.5 v to v cc + 0.5 v input voltage ....................................... ?0.5 v to v cc + 0.5 v transient voltage (< 20 ns) on any pin to ground potential ................. ?2.0 v to v cc + 2.0 v package power dissipation capability (t a = 25 c) ................................................. 1.0 w surface mount pb soldering temperature (3 seconds) ........ .............. .............. ..... +260 ? c dc output current (1 output at a time, 1 s duration) ... 15 ma static discharge voltage (per mil-std-883, method 3015) .............. ........... > 2001 v latch up current .................................................... > 200 ma operating range range ambient temperature v cc industrial ?40 ? c to +85 ? c 4.5 v to 5.5 v dc electrical characteristics over the operating range parameter description test conditions min typ [9] max unit v cc power supply 4.5 5.0 5.5 v i cc1 average v cc current t rc = 25 ns t rc = 45 ns values obtained without output loads (i out = 0 ma) ??70 52 ma ma i cc2 average v cc current during store all inputs don?t care, v cc = max average current for duration t store ??10ma i cc3 average v cc current at t rc = 200 ns, v cc(typ) , 25 c all inputs cycling at cmos levels. values obtained without output loads (i out = 0 ma). ?35?ma i cc4 average v cap current during autostore cycle all inputs don?t care. average current for duration t store ??8ma i sb v cc standby current ce > (v cc ? 0.2 v). v in < 0.2 v or > (v cc ? 0.2 v). standby current level after nonvolatile cycle is complete. inputs are static. f = 0 mhz. ??8ma i ix [10] input leakage current (except hsb ) v cc = max, v ss < v in < v cc ?1 ? +1 ? a input leakage current (for hsb )v cc = max, v ss < v in < v cc ?100 ? +1 ? a i oz off-state output leakage current v cc = max, v ss < v out < v cc , ce or oe > v ih or we < v il ?1 ? +1 ? a v ih input high voltage 2.0 ? v cc + 0.5 v v il input low voltage v ss ? 0.5 ? 0.8 v v oh output high voltage i out = ?2 ma 2.4 ? ? v v ol output low voltage i out = 4 ma ? ? 0.4 v notes 9. typical values are at 25 c, v cc = v cc(typ) . not 100% tested. 10. the hsb pin has i out = ?2 a for v oh of 2.4 v when both active high and low drivers are disabled. when they are enabled standard v oh and v ol are valid. this parameter is characterized but not tested. cy14e256la document number: 001-54952 rev. *j page 8 of 19 v cap [11] storage capacitor between v cap pin and v ss 61 68 180 ? f v vcap [12, 13] maximum voltage driven on v cap pin by the device v cc = max ? ? v cc ? 0.5 v dc electrical characteristics (continued) over the operating range parameter description test conditions min typ [9] max unit data retention and endurance over the operating range parameter description min unit data r data retention 20 years nv c nonvolatile store operations 1,000 k capacitance parameter [13] description test conditions max unit c in input capacitance (except hsb )t a = 25 ? c, f = 1 mhz, v cc = v cc(typ) 7pf input capacitance (for hsb )8pf c out output capacitance (except hsb ) 7 pf output capacitance (for hsb ) 8 pf thermal resistance parameter [13] description test conditions 44-pin tsop ii 32-pin soic unit ? ja thermal resistance (junction to ambient) test conditions follow standard test methods and procedures for measuring thermal impedance, in accordance with eia/jesd51. 41.74 41.55 ? c/w ? jc thermal resistance (junction to case) 11.90 24.43 ? c/w notes 11. min v cap value guarantees that there is a sufficient charge available to complete a successful autostore operation. max v cap value guarantees that the capacitor on v cap is charged to a minimum voltage during a power-up recall cycle so that an immediate power-down cycle can complete a successful autostore. therefore it is always recommended to use a capacitor within the specified min and max limits. refer application note an43593 for more details on v cap options. 12. maximum voltage on v cap pin (v vcap ) is provided for guidance when choosing the v cap capacitor. the voltage rating of the v cap capacitor across the operating temperature range should be higher than the v vcap voltage. 13. these parameters are guaranteed by design and are not tested cy14e256la document number: 001-54952 rev. *j page 9 of 19 ac test conditions input pulse levels .................................................0 v to 3 v input rise and fall times (10% to 90%) .................... < 3 ns input and output timing reference levels .................. 1.5 v ac test loads figure 3. ac test loads 5.0 v output 5 pf r1 r2 512 ? 5.0 v output 30 pf r1 r2 512 ? for tri-state specs 963 ? 963 ? cy14e256la document number: 001-54952 rev. *j page 10 of 19 ac switching characteristics over the operating range parameters [14] description 25 ns 45 ns unit cypress parameter alt parameter min max min max sram read cycle t ace t acs chip enable access time ? 25 ? 45 ns t rc [15] t rc read cycle time 25 ? 45 ? ns t aa [16] t aa address access time ? 25 ? 45 ns t doe t oe output enable to data valid ? 12 ? 20 ns t oha [16] t oh output hold after address change 3 ? 3 ? ns t lzce [17, 18] t lz chip enable to output active 3 ? 3 ? ns t hzce [17, 18] t hz chip disable to output inactive ? 10 ? 15 ns t lzoe [17, 18] t olz output enable to output active 0 ? 0 ? ns t hzoe [17, 18] t ohz output disable to output inactive ? 10 ? 15 ns t pu [17] t pa chip enable to power active 0 ? 0 ? ns t pd [17] t ps chip disable to power standby ? 25 ? 45 ns sram write cycle t wc t wc write cycle time 25 ? 45 ? ns t pwe t wp write pulse width 20 ? 30 ? ns t sce t cw chip enable to end of write 20 ? 30 ? ns t sd t dw data setup to end of write 10 ? 15 ? ns t hd t dh data hold after end of write 0 ? 0 ? ns t aw t aw address setup to end of write 20 ? 30 ? ns t sa t as address setup to start of write 0 ? 0 ? ns t ha t wr address hold after end of write 0 ? 0 ? ns t hzwe [17, 18, 19] t wz write enable to output disable ? 10 ? 15 ns t lzwe [17, 18] t ow output active after end of write 3 ? 3 ? ns switching waveforms figure 4. sram read cycle #1 (address controlled) [15, 16, 20] address data output address valid previous data valid output data valid t rc t aa t oha notes 14. test conditions assume signal transition time of 3 ns or less, timing reference levels of v cc /2, input pulse levels of 0 to v cc (typ), and output loading of the specified i ol /i oh and load capacitance shown in figure . 15. we must be high during sram read cycles. 16. device is continuously selected with ce and oe low. 17. these parameters are guaranteed by design and are not tested. 18. measured 200 mv from steady state output voltage. 19. if we is low when ce goes low, the outputs remain in the high impedance state. 20. hsb must remain high during read and write cycles. cy14e256la document number: 001-54952 rev. *j page 11 of 19 figure 5. sram read cycle #2 (ce and oe controlled) [21, 22] figure 6. sram write cycle #1 (we controlled) [22, 23, 24] figure 7. sram write cycle #2 (ce controlled) [22, 23, 24] switching waveforms (continued) address valid address data output output data valid standby active high impedance ce oe i cc t hzce t rc t ace t aa t lzce t doe t lzoe t pu t pd t hzoe data output data input input data valid high impedance address valid address previous data t wc t sce t ha t aw t pwe t sa t sd t hd t hzwe t lzwe we ce data output data input input data valid high impedance address valid address t wc t sd t hd we ce t sa t sce t ha t pwe note 21. we must be high during sram read cycles. 22. hsb must remain high during read and write cycles. 23. if we is low when ce goes low, the outputs remain in the high impedance state. 24. ce or we must be > v ih during address transitions. cy14e256la document number: 001-54952 rev. *j page 12 of 19 autostore/power-up recall over the operating range parameter description cy14e256la unit min max t hrecall [25] power-up recall duration ? 20 ms t store [26] store cycle duration ? 8 ms t delay [27] time allowed to comple te sram write cycle ? 25 ns v switch low voltage trigger level ? 4.4 v t vccrise [28] v cc rise time 150 ? s v hdis [28] hsb output disable voltage ? 1.9 v t lzhsb [28] hsb to output active time ? 5 s t hhhd [28] hsb high active time ? 500 ns switching waveforms figure 8. autostore or power-up recall [29] v switch v hdis t vccrise t store t store t hhhd t hhhd t delay t delay t lzhsb t lzhsb t hrecall t hrecall hsb out autostore power- up recall read & write inhibited (rwi) power-up recall read & write brown out autostore power-up recall read & write power down autostore note note note note v cc 26 26 30 30 notes 25. t hrecall starts from the time v cc rises above v switch . 26. if an sram write has not taken place since the last nonvolatile cycle, no autostore or hardware store takes place. 27. on a hardware store and autostore initiation, sram write operation continues to be enabled for time t delay . 28. these parameters are guaranteed by design and are not tested. 29. read and write cycles are ignored during store, recall, and while v cc is less than v switch . 30. during power-up and power-down, hsb glitches when hsb pin is pulled up through an external resistor. cy14e256la document number: 001-54952 rev. *j page 13 of 19 software controlled store/recall cycle over the operating range parameter [31, 32] description 25 ns 45 ns unit min max min max t rc store/recall initiation cycle time 25 ? 45 ? ns t sa address setup time 0 ? 0 ? ns t cw clock pulse width 20 ? 30 ? ns t ha address hold time 0 ? 0 ? ns t recall recall duration ? 200 ? 200 s switching waveforms figure 9. ce and oe controlled software store/recall cycle [32] figure 10. autostore enable / disable cycle [32] t rc t rc t sa t cw t cw t sa t ha t lzce t hzce t ha t ha t ha t store /t recall t hhhd t lzhsb high impedance address #1 address #6 address ce oe hsb (store only) dq (data) rwi t delay note 33 t rc t rc t sa t cw t cw t sa t ha t lzce t hzce t ha t ha t ha t delay address #1 address #6 address ce oe dq (data) t ss note rwi 33 notes 31. the software sequence is clocked with ce controlled or oe controlled reads. 32. the six consecutive addresses must be read in the order listed in table 1 on page 5 . we must be high during all six consecutive cycles. 33. dq output data at the sixth read may be invalid since the output is disabled at t delay time. cy14e256la document number: 001-54952 rev. *j page 14 of 19 hardware store cycle over the operating range parameter description cy14e256la unit min max t dhsb hsb to output active time when write latch not set ? 25 ns t phsb hardware store pulse width 15 ? ns t ss [34, 35] soft sequence processing time ? 100 ? s switching waveforms figure 11. hardware store cycle [36] figure 12. soft sequence processing [34, 35] ~ ~ ~ ~ hsb (in) hsb (out) so rwi hsb (in) hsb (out) rwi t hhhd t store t phsb t delay t lzhsb t delay t dhsb t dhsb t phsb hsb pin is driven high to v ccq only by internal 100 k : resistor, hsb driver is disabled sram is disabled as long as hsb (in) is driven low. write latch not set write latch set address #1 address #6 address #1 address #6 soft sequence command t ss t ss ce address v cc t sa t cw soft sequence command t cw notes 34. this is the amount of time it takes to take action on a soft sequence command. vcc power must remain high to effectively reg ister command. 35. commands such as store and recall lock out i/o until operation is complete which further increases this time. see the specif ic command. 36. if an sram write has not taken place since the last nonvol atile cycle, no autostore or hardware store takes place. cy14e256la document number: 001-54952 rev. *j page 15 of 19 ordering code definitions truth table for sram operations hsb must remain high for sram operations. table 2. truth table ce we oe inputs/outputs mode power h x x high z deselect/power-down standby l h l data out (dq 0 ?dq 7 ) read active l h h high z output disabled active l l x data in (dq 0 ?dq 7 ) write active ordering information speed (ns) ordering code package diagram package type operating range 25 cy14e256la-sz25xit 51-85127 32-pin soic industrial cy14e256la-sz25xi 45 CY14E256LA-SZ45XIt CY14E256LA-SZ45XI all the mentioned parts are pb-free. option: t ? tape and reel blank ? std. speed: 25 to 25 ns data bus: l ? 8 density: 256 ? 256 kb voltage: e ? 5.0 v cypress cy 14 e 256 l a - zs 25 x i t 14 ? nvsram pb-free package: zs ? 44-pin tsop ii 45 to 45 ns die revision: blank ? no rev a ? 1 st rev temperature: i ? industrial (?40 to 85 o c) sz ? 32-pin soic cy14e256la document number: 001-54952 rev. *j page 16 of 19 package diagrams figure 13. 44-pin tsop ii package outline, 51-85087 figure 14. 32-pin soic (300 mil) package outline, 51-85127 51-85087 *e 51-85127 *c cy14e256la document number: 001-54952 rev. *j page 17 of 19 acronyms document conventions units of measure acronym description ce chip enable cmos complementary metal oxide semiconductor eia electronic industries alliance hsb hardware store busy i/o input/output jedec joint electron devices engineering council nvsram non-volatile static random access memory oe output enable rohs restriction of hazardous substances rwi read and write inhibited soic small outline integrated circuit sram static random access memory tsop thin small outline package we write enable symbol unit of measure c degree celsius k ? kilohm mhz megahertz ? a microampere ? f microfarad ? s microsecond ma milliampere ms millisecond mv millivolt ns nanosecond ? ohm % percent pf picofarad ps picosecond v volt w watt cy14e256la document number: 001-54952 rev. *j page 18 of 19 document history page document title: cy14e256la, 256-kbit (32 k 8) nvsram document number: 001-54952 revision ecn orig. of change submission date description of change ** 2748216 gvch / pyrs 08/04/09 new datasheet *a 2772059 gvch 09/30/09 updated software store, recall and autostore enable, disable soft sequence *b 2829117 gvch 12/16/09 updated store cycles to quantumtrap from 200k to 1 million added contents . moved to external web. *c 2891356 gvch 03/12/10 removed inactive parts from ordering information table. updated links in sales, solutions, and legal information . *d 2922858 gvch 04/26/10 table 1 : added more clarity on hsb pin operation hardware store operation : added more clarity on hsb pin operation updated hsb pin operation in figure 8 and updated footnote 21 updated package diagram 51-85087 *e 3030490 gvch 09/15/10 change: i sb and i cc4 max value from 5 ma to 8 ma. areas affected: dc electrical characteristics on page 7 . change: template and styles update. areas affected: entire datasheet *f 3143330 gvch 01/17/2011 fixed typo in figure 8 . *g 3219793 gvch 04/08/2011 logic block diagram : fixed typo *h 3315247 gvch 07/15/2011 updated dc electrical characteristics (added note 11 and referred the same note in v cap parameter). updated capacitance (included input capacitance (for hsb ) and output capacitance (for hsb )). updated ac switching characteristics (added note 14 and referred the same note in parameters). *i 3660776 gvch 06/29/2012 updated dc electrical characteristics (added v vcap parameter and its details, added note 12 and referred the same note in v vcap parameter, also referred note 13 in v vcap parameter). updated package diagrams (spec 51-85127 (changed revision from *b to *c)). *j 3759425 gvch 09/28/2012 updated maximum ratings (removed ?ambient temperature with power applied? and included ?maximum junction temperature?). updated package diagrams (spec 51-85087 (changed revision from *d to *e)). document number: 001-54952 rev. *j revised september 28, 2012 page 19 of 19 all products and company names mentioned in this document may be the trademarks of their respective holders. cy14e256la ? cypress semiconductor corporation, 2009-2012. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface 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